23 search results - page 1 / 5 » Timing-driven global routing with efficient buffer insertion |
DAC
2009
ACM
14 years 5 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
-- Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becom...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wireleng...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...