188 search results - page 1 / 38 » Timing-driven optimization using lookahead logic circuits |
DAC
2009
ACM
14 years 6 months ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
FPGA
1999
ACM
13 years 9 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper addresses the issue of timing driven gate duplication for delay optimization. Gate duplication has been used extensively for cutset minimization but the usefulness in m...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
This work studies the optimality and stability of timing-driven placement algorithms. The contributions of this work include two parts: 1) We develop an algorithm for generating s...