25 search results - page 5 / 5 » Timing-driven placement by grid-warping |
ISPD
1997
ACM
13 years 9 months ago
1997
ACM
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
ARITH
1999
IEEE
13 years 9 months ago
1999
IEEE
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
ISPD
2005
ACM
13 years 10 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...