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» Tolerance Models in Hardware Description Languages
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DAC
1997
ACM
13 years 9 months ago
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development to...
Mark R. Hartoog, James A. Rowson, Prakash D. Reddy...
MOMPES
2008
IEEE
13 years 11 months ago
Architectural Concurrency Equivalence with Chaotic Models
During its lifetime, embedded systems go through multiple changes to their runtime architecture. That is, threads, processes, and processor are added or removed to/from the softwa...
Dionisio de Niz
DSD
2007
IEEE
119views Hardware» more  DSD 2007»
13 years 11 months ago
Online Protocol Testing for FPGA Based Fault Tolerant Systems
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
Jiri Tobola, Zdenek Kotásek, Jan Korenek, T...
MEMOCODE
2005
IEEE
13 years 11 months ago
Extended abstract: a race-free hardware modeling language
We describe race-free properties of a hardware description language called GEZEL. The language describes networks of cycle-true finite-state-machines with datapaths (FSMDs). We de...
Patrick Schaumont, Sandeep K. Shukla, Ingrid Verba...
ISCA
2002
IEEE
141views Hardware» more  ISCA 2002»
13 years 5 months ago
SADL: Simulation Architecture Description Language
This paper introduces the Simulation Architecture Description Language (SADL) developed at the National Aeronautics and Space Administration's Marshall Space Flight Center to...
Kenneth G. Ricks, John M. Weirs, B. Earl Wells