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DFT
2006
IEEE
74views VLSI» more  DFT 2006»
13 years 12 months ago
Recovery Mechanisms for Dual Core Architectures
Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic informa...
Christian El Salloum, Andreas Steininger, Peter Tu...
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
14 years 7 days ago
Software Protection Mechanisms for Dependable Systems
We expect that in future commodity hardware will be used in safety critical applications. But the used commodity microprocessors will become less reliable because of decreasing fe...
Ute Wappler, Martin Muller
IEEEPACT
2007
IEEE
14 years 2 days ago
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
Brian Greskamp, Josep Torrellas
IPPS
1998
IEEE
13 years 10 months ago
An Efficient RMS Admission Control and Its Application to Multiprocessor Scheduling
A real-time system must execute functionally correct computations in a timely manner. In order to guarantee that all tasks accepted in the system will meet their timing requiremen...
Sylvain Lauzac, Rami G. Melhem, Daniel Mossé...
DSN
2007
IEEE
14 years 3 days ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...