26 search results - page 2 / 6 » Total Power Minimization in Glitch-Free CMOS Circuits Consid... |
ASPDAC
2010
ACM
13 years 3 months ago
2010
ACM
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
ESSCIRC
2011
12 years 5 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
ICCD
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
TVLSI
2008
13 years 5 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...