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» Towards Metaprogramming for Parallel Systems on a Chip
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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 2 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ASPLOS
2012
ACM
12 years 1 months ago
Chameleon: operating system support for dynamic processors
The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to para...
Sankaralingam Panneerselvam, Michael M. Swift
CASES
2006
ACM
13 years 11 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
PPOPP
2005
ACM
13 years 10 months ago
Exposing speculative thread parallelism in SPEC2000
As increasing the performance of single-threaded processors becomes increasingly difficult, consumer desktop processors are moving toward multi-core designs. One way to enhance th...
Manohar K. Prabhu, Kunle Olukotun
ISHPC
2000
Springer
13 years 8 months ago
The New DRAM Interfaces: SDRAM, RDRAM and Variants
For the past two decades, developments in DRAM technology, the primary technology for the main memory of computers, have been directed towards increasing density. As a result 256 M...
Brian Davis, Bruce L. Jacob, Trevor N. Mudge