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» Transformed pseudo-random patterns for BIST
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ITC
1995
IEEE
104views Hardware» more  ITC 1995»
13 years 8 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
DSD
2007
IEEE
140views Hardware» more  DSD 2007»
13 years 11 months ago
Pseudo-Random Pattern Generator Design for Column-Matching BIST
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
Petr Fiser
MTDT
2000
IEEE
129views Hardware» more  MTDT 2000»
13 years 9 months ago
Using GLFSRs for Pseudo-Random Memory BIST
In this work, we present the application of Generalized Linear Feedback Shift Registers (GLFSRs) for generation of patterns for pseudo-random memory Built-In SelfTest (BIST). Rece...
Michael Redeker, Markus Rudack, Thomas Lobbe, Dirk...
DSD
2005
IEEE
96views Hardware» more  DSD 2005»
13 years 6 months ago
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
Peter Filter, Hana Kubatova
IOLTS
2000
IEEE
105views Hardware» more  IOLTS 2000»
13 years 9 months ago
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...