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EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
13 years 8 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
ASPDAC
1995
ACM
108views Hardware» more  ASPDAC 1995»
13 years 8 months ago
Synthesis-for-testability using transformations
- We address the problem of transforming a behavioral specification so that synthesis of a testable implementation from the new specification requires significantly less area and ...
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
DAC
1994
ACM
13 years 8 months ago
Optimizing Resource Utilization and Testability Using Hot Potato Techniques
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...
Miodrag Potkonjak, Sujit Dey
ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
13 years 8 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...