1640 search results - page 3 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
DSD
2007
IEEE
13 years 9 months ago
2007
IEEE
We present a component-based framework and its supporting simulation tool for joint software-hardware modelling and performance analysis of multiprocessor embedded systems. This j...
ICASSP
2009
IEEE
14 years 2 days ago
2009
IEEE
In this paper, block diagonal linear discriminant analysis (BDLDA) is improved and applied to gene expression data. BDLDA is a classification tool with embedded feature selection...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...