Sciweavers

Share
26 search results - page 1 / 6
» Translation Validation of High-Level Synthesis
Sort
View
TCAD
2010
121views more  TCAD 2010»
11 years 4 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
CAV
2008
Springer
131views Hardware» more  CAV 2008»
11 years 11 months ago
Validating High-Level Synthesis
The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the pro...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta
FDL
2007
IEEE
12 years 3 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
TVLSI
2008
120views more  TVLSI 2008»
11 years 9 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
CARDIS
2004
Springer
150views Hardware» more  CARDIS 2004»
12 years 2 months ago
Enforcing High-Level Security Properties for Applets
Smart card applications often handle privacy-sensitive information, and therefore must obey certain security policies. Typically, such policies are described as high-level security...
Mariela Pavlova, Gilles Barthe, Lilian Burdy, Mari...
books