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» Transmission line design of clock trees
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ICCAD
2002
IEEE
129views Hardware» more  ICCAD 2002»
14 years 1 months ago
Transmission line design of clock trees
We investigate appropriate regimes for transmission line propagation of signals on digital integrated circuits. We start from exact solutions to the transmission line equations pr...
Rafael Escovar, Roberto Suaya
ICCAD
1993
IEEE
123views Hardware» more  ICCAD 1993»
13 years 8 months ago
Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...
Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi
DATE
2008
IEEE
157views Hardware» more  DATE 2008»
13 years 11 months ago
Clock Distribution Scheme using Coplanar Transmission Lines
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
Victor H. Cordero, Sunil P. Khatri
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
13 years 10 months ago
Design methodology for global resonant H-tree clock distribution networks
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
Jonathan Rosenfeld, Eby G. Friedman
ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
13 years 10 months ago
Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers
Abstract- This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown t...
Soroush Abbaspour, Massoud Pedram, Payam Heydari