22 search results - page 1 / 5 » Two-level microprocessor-accelerator partitioning |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
COLING
1996
13 years 6 months ago
1996
This paper describes an algorithm for the compilation of a two (or more) level orthographic or phonological rule notation into finite state transducers. The notation is an alterna...
IPPS
2002
IEEE
13 years 9 months ago
2002
IEEE
A new method, namely the Parallel Two-Level Hybrid (PTH) method, is developed to solve tridiagonal systems on parallel computers. PTH is designed based on Parallel Diagonal Domina...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
ASYNC
1998
IEEE
13 years 9 months ago
1998
IEEE
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to heuristic...