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» Understanding POWER multiprocessors
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HPCA
2006
IEEE
14 years 6 months ago
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...
David A. Penry, Daniel Fay, David Hodgdon, Ryan We...
CAL
2006
13 years 5 months ago
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial ...
T. Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Val...
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
13 years 3 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
ICALP
2010
Springer
13 years 9 months ago
Scalably Scheduling Power-Heterogeneous Processors
We show that a natural online algorithm for scheduling jobs on a heterogeneous multiprocessor, with arbitrary power functions, is scalable for the objective function of weighted ï¬...
Anupam Gupta, Ravishankar Krishnaswamy, Kirk Pruhs
ISQED
2010
IEEE
161views Hardware» more  ISQED 2010»
13 years 7 months ago
Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint
- In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power con...
Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedr...