24 search results - page 2 / 5 » Unified adaptivity optimization of clock and logic signals |
FPGA
1997
ACM
13 years 9 months ago
1997
ACM
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
ISPD
1999
ACM
13 years 9 months ago
1999
ACM
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
GLOBECOM
2006
IEEE
13 years 10 months ago
2006
IEEE
— Implementing a multi-tone (MT) architecture for high-speed backplane electrical links is difficult given the tight power and complexity constraints in this application. This pa...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...