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» Using FORAY Models to Enable MPSoC Memory Optimizations
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TCAD
2008
110views more  TCAD 2008»
13 years 3 months ago
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC inte...
Shankar Mahadevan, Federico Angiolini, Jens Spars&...
LCTRTS
2010
Springer
13 years 11 months ago
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
Ines Viskic, Lochi Lo Chi Yu Lo, Daniel Gajski
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
13 years 10 months ago
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations
In today’s embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the u...
Ilya Issenin, Nikil D. Dutt
DAC
2006
ACM
13 years 6 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...