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ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
FCCM
2002
IEEE
208views VLSI» more  FCCM 2002»
13 years 10 months ago
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...
Nicholas Weaver, John Wawrzynek
GECCO
2005
Springer
131views Optimization» more  GECCO 2005»
13 years 10 months ago
Multipopulation cooperative coevolutionary programming (MCCP) to enhance design innovation
This paper describes the development of an evolutionary algorithm called Multipopulation Cooperative Coevolutionary Programming (MCCP) that extends Genetic Programming (GP) to sea...
Emily M. Zechman, S. Ranji Ranjithan
ISSS
1997
IEEE
103views Hardware» more  ISSS 1997»
13 years 9 months ago
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
Chih-Tung Chen, Kayhan Küçük&cced...
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
13 years 11 months ago
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
Saraju P. Mohanty