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TCAD
2011
8 years 2 months ago
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhig...
ENTCS
2008
110views more  ENTCS 2008»
8 years 7 months ago
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
JunBok You, Yang Xu, Hosuk Han, Kenneth S. Stevens
ITC
2003
IEEE
110views Hardware» more  ITC 2003»
9 years 15 days ago
An extension to JTAG for at-speed debug on a system
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
Leon van de Logt, Frank van der Heyden, Tom Waayer...
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
8 years 11 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
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