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» Using Little's Law to estimate cycle time and cost
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VTS
2007
IEEE
203views Hardware» more  VTS 2007»
13 years 11 months ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba
ICDM
2007
IEEE
131views Data Mining» more  ICDM 2007»
13 years 9 months ago
Predicting and Optimizing Classifier Utility with the Power Law
When data collection is costly and/or takes a significant amount of time, an early prediction of the classifier performance is extremely important for the design of the data minin...
Mark Last
VLSI
2007
Springer
13 years 11 months ago
Estimating design time for system circuits
System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to estimate how much time it ...
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian G...
RAS
2008
127views more  RAS 2008»
13 years 4 months ago
Online generation of cyclic leg trajectories synchronized with sensor measurement
The generation of trajectories for a biped robot is a problem which has been largely studied for several years, and many satisfying off-line solutions exist for steady-state walki...
Rodolphe Héliot, Bernard Espiau
DFT
2006
IEEE
92views VLSI» more  DFT 2006»
13 years 11 months ago
Low-Cost Hardening of Image Processing Applications Against Soft Errors
Image processing systems are increasingly used in safetycritical applications, and their hardening against soft errors becomes an issue. We propose a methodology to identify soft ...
Ilia Polian, Bernd Becker, Masato Nakasato, Satosh...