17 search results - page 2 / 4 » Using Process-Level Redundancy to Exploit Multiple Cores for... |
ASPLOS
2006
ACM
13 years 8 months ago
2006
ACM
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...
ASPLOS
2006
ACM
13 years 10 months ago
2006
ACM
Redundant threading architectures duplicate all instructions to detect and possibly recover from transient faults. Several lighter weight Partial Redundant Threading (PRT) archite...
TCAD
2010
12 years 11 months ago
2010
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
RTS
2006
13 years 4 months ago
2006
Abstract. The Time-Triggered Architecture, as architecture for safety-critical realtime applications, incorporates fault-tolerance mechanisms to ensure correct system operation des...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...