259 search results - page 1 / 52 » Using Transformations and Verification in Circuit Design |
LARCH
1992
13 years 9 months ago
1992
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
CAV
2010
Springer
13 years 5 months ago
2010
Springer
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...
VTS
2000
IEEE
13 years 8 months ago
2000
IEEE
