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» VAPRES: A Virtual Architecture for Partially Reconfigurable ...
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ARC
2007
Springer
150views Hardware» more  ARC 2007»
13 years 8 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
ERSA
2006
100views Hardware» more  ERSA 2006»
13 years 6 months ago
Relocation and Defragmentation for Heterogeneous Reconfigurable Systems
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
Markus Koester, Heiko Kalte, Mario Porrmann
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
MEMOCODE
2008
IEEE
13 years 11 months ago
Virtual prototyping AADL architectures in a polychronous model of computation
While synchrony and asynchrony are two distinct concepts of concurrency theory, effective and formally defined embedded system design methodologies usually mix the best from both...
Ma Yue, Jean-Pierre Talpin, Thierry Gautier
ENTCS
2008
106views more  ENTCS 2008»
13 years 4 months ago
Modelling Adaptive Systems in ForSyDe
Emerging architectures such as partially reconfigurable FPGAs provide a huge potential for adaptivity in the area of embedded systems. Since many system functions are only execute...
Ingo Sander, Axel Jantsch