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TVLSI
2008
133views more  TVLSI 2008»
13 years 4 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
13 years 10 months ago
Reconfigurable Fast Memory Management System Design for Application Specific Processors
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...
S. Kagan Agun, J. Morris Chang
ERSA
2006
70views Hardware» more  ERSA 2006»
13 years 6 months ago
Differential Reconfiguration Architecture suitable for a Holographic Memory
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobaya...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 8 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
FCCM
2002
IEEE
133views VLSI» more  FCCM 2002»
13 years 9 months ago
Reconfigurable Shape-Adaptive Template Matching Architectures
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...
Jörn Gause, Peter Y. K. Cheung, Wayne Luk