428 search results - page 1 / 86 » Validating High-Level Synthesis |
CAV
2008
Springer
13 years 6 months ago
2008
Springer
The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the pro...
TCAD
2010
12 years 11 months ago
2010
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
FDL
2007
IEEE
13 years 10 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
TVLSI
2008
13 years 4 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
ASYNC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...