29 search results - page 2 / 6 » Variable Resizing for Area Improvement in Behavioral Synthes... |
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
TCAD
1998
13 years 4 months ago
1998
— We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG’s) during the high-level synthesis of data-pathinten...