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TVLSI
2008
176views more  TVLSI 2008»
13 years 4 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
TVLSI
2010
12 years 11 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
FDTC
2011
Springer
267views Cryptology» more  FDTC 2011»
12 years 4 months ago
An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs
Abstract—The literature about fault analysis typically describes fault injection mechanisms, e.g. glitches and lasers, and cryptanalytic techniques to exploit faults based on som...
Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwh...
ET
2010
122views more  ET 2010»
13 years 2 months ago
Fault Models for Quantum Mechanical Switching Networks
This work justifies several quantum gate level fault models and discusses the causal error mechanisms thwarting correct function. A quantum adaptation of the classical test set gen...
Jacob D. Biamonte, Jeff S. Allen, Marek A. Perkows...
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
13 years 10 months ago
Generation of broadside transition fault test sets that detect four-way bridging faults
Generation of n -detection test sets is typically done for a single fault model. In this work we investigate the generation of n -detection test sets by pairing each fault of a ta...
Irith Pomeranz, Sudhakar M. Reddy