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» Variation-aware routing for FPGAs
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FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
13 years 11 months ago
Variation-aware routing for FPGAs
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Satish Sivaswamy, Kia Bazargan
ISVLSI
2006
IEEE
85views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Variation Aware Placement for FPGAs
Suresh Srinivasan, Narayanan Vijaykrishnan
ISPD
2003
ACM
106views Hardware» more  ISPD 2003»
13 years 10 months ago
Process variation aware clock tree routing
Bing Lu, Jiang Hu, Gary Ellis, Haihua Su
FPL
2006
Springer
137views Hardware» more  FPL 2006»
13 years 8 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
FPGA
2012
ACM
300views FPGA» more  FPGA 2012»
12 years 17 days ago
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemente...
Yehdhih Ould Mohammed Moctar, Nithin George, Hadi ...