49 search results - page 1 / 10 » Vdd programmability to reduce FPGA interconnect power |
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
14 years 5 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...