7 search results - page 1 / 2 » Verification of the Generic Architecture of a Memory Circuit... |
FORMATS
2006
Springer
13 years 8 months ago
2006
Springer
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
ENTCS
2006
13 years 4 months ago
2006
The application of formal methods to analog and mixed signal circuits requires efficient methods tructing abstractions of circuit behaviors. This paper concerns the verification o...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...