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» Verification via Structure Simulation
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CAV
2004
Springer
96views Hardware» more  CAV 2004»
13 years 8 months ago
Verification via Structure Simulation
Neil Immerman, Alexander Moshe Rabinovich, Thomas ...
EURODAC
1995
IEEE
180views VHDL» more  EURODAC 1995»
13 years 8 months ago
Integration of VHDL into a system design environment
Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers...
Ludwig Schwoerer, Matthias Lück, Hartmut Schr...