69 search results - page 13 / 14 » WCET estimation for executables in the presence of data cach... |
MICRO
2002
IEEE
13 years 11 months ago
2002
IEEE
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
RTAS
2010
IEEE
13 years 4 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
FPL
2009
Springer
13 years 10 months ago
2009
Springer
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
WMPI
2004
ACM
13 years 11 months ago
2004
ACM
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
HIPEAC
2007
Springer
14 years 4 days ago
2007
Springer
A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of ...