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DATE
1998
IEEE
91views Hardware» more  DATE 1998»
13 years 10 months ago
Interconnect Tuning Strategies for High-Performance Ics
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahu...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
13 years 11 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....
CODES
2004
IEEE
13 years 9 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
CASES
2006
ACM
13 years 9 months ago
Probabilistic arithmetic and energy efficient embedded signal processing
Probabilistic arithmetic, where the ith output bit of addition and multiplication is correct with a probability pi, is shown to be a vehicle for realizing extremely energy-efficie...
Jason George, B. Marr, Bilge E. S. Akgul, Krishna ...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 5 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri