38 search results - page 2 / 8 » Wire-driven microarchitectural design space exploration |
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
HPCA
2007
IEEE
14 years 4 months ago
2007
IEEE
We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to ident...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout....
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
13 years 8 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....