85 search results - page 17 / 17 » Wrong-path Instruction Prefetching |
CF
2004
ACM
13 years 11 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
HIPEAC
2009
Springer
13 years 10 months ago
2009
Springer
Abstract. Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application charac...
ISCA
2000
IEEE
13 years 10 months ago
2000
IEEE
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
JPDC
2007
13 years 5 months ago
2007
The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch...