19 search results - page 2 / 4 » Yield Estimation of VLSI Circuits with Downscaled Layouts |
GLVLSI
2009
IEEE
13 years 9 months ago
2009
IEEE
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envel...
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layou...
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those prop...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...