5 search results - page 1 / 1 » Yield enhancement of asynchronous logic circuits through 3-d... |
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
TCAD
2002
13 years 4 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...