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APCCAS
2006
IEEE
224views Hardware» more  APCCAS 2006»
13 years 7 months ago
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment
Abstract-- Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory pl...
Masanori Hariyama, Michitaka Kameyama
APCCAS
2006
IEEE
254views Hardware» more  APCCAS 2006»
13 years 11 months ago
Redundant Adders Consume Less Energy
— We conduct a complete analysis of the effect of digit redundancy in adders on their delay, power, energy, and energy-delay product. To our knowledge, this is the first such de...
Kavallur Gopi Smitha, H. A. H. Fahmy, A. Prasad Vi...
APCCAS
2006
IEEE
256views Hardware» more  APCCAS 2006»
13 years 11 months ago
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, ...
APCCAS
2006
IEEE
264views Hardware» more  APCCAS 2006»
13 years 11 months ago
FPGA-Based Design of a Pulsed-OFDM System
—An enhancement to the MB-OFDM system, known as Pulsed-OFDM, has been proposed to reduce the complexity and power consumption of the transceiver without sacrificing performance. ...
Kai-Chuan Chang, Gerald E. Sobelman
APCCAS
2006
IEEE
290views Hardware» more  APCCAS 2006»
13 years 9 months ago
An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications
in this paper, a new CAVLC decoding architecture with a soft-input design concept is proposed. We introduce the soft-decision information to localize the erroneous position at macr...
Tsu-Ming Liu, Chen-Yi Lee