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ASAP
2008
IEEE
118views Hardware» more  ASAP 2008»
13 years 11 months ago
Bit matrix multiplication in commodity processors
Registers in processors generally contain words or, with the addition of multimedia extensions, short vectors of subwords of bytes or 16-bit elements. In this paper, we view the c...
Yedidya Hilewitz, Cédric Lauradoux, Ruby B....
ASAP
2008
IEEE
82views Hardware» more  ASAP 2008»
13 years 11 months ago
Run-time thread sorting to expose data-level parallelism
We address the problem of data parallel processing for computational quantum chemistry (CQC). CQC is a computationally demanding tool to study the electronic structure of molecule...
Tirath Ramdas, Gregory K. Egan, David Abramson, Ki...
ASAP
2008
IEEE
110views Hardware» more  ASAP 2008»
13 years 11 months ago
Design space exploration of a cooperative MIMO receiver for reconfigurable architectures
Cooperative MIMO is a new technique that allows disjoint wireless communication nodes (e.g. wireless sensors) to form a virtual antenna array to increase bandwidth, reliability an...
Shahnam Mirzaei, Ali Irturk, Ryan Kastner, Brad T....
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
13 years 11 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
13 years 6 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...