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DAC
1994
ACM
13 years 9 months ago
RC Interconnect Optimization Under the Elmore Delay Model
An e cient solution to the wire sizing problem WSP usingthe Elmoredelaymodelisproposed. Two formulations of the problem are put forth: in the rst, the minimum interconnect delay i...
Sachin S. Sapatnekar
DAC
1994
ACM
13 years 9 months ago
Fitting Formal Methods into the Design Cycle
This tutorial introduces several methods of formal hardware veri cation that could potentially have a practical impact on the design process. The measure of success in integrating...
Kenneth L. McMillan
DAC
1994
ACM
13 years 9 months ago
Boolean Matching Using Generalized Reed-Muller Forms
-- In this paper we present a new method for Boolean matching of completely specified Boolean functions. The canonical Generalized Reed-Muller forms are used as a powerful analysis...
Chien-Chung Tsai, Malgorzata Marek-Sadowska
DAC
1994
ACM
13 years 9 months ago
Minimal Delay Interconnect Design Using Alphabetic Trees
Abstract - We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner a...
Ashok Vittal, Malgorzata Marek-Sadowska
DAC
1994
ACM
13 years 9 months ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
Horng-Fei Jyu, Sharad Malik