An e cient solution to the wire sizing problem WSP usingthe Elmoredelaymodelisproposed. Two formulations of the problem are put forth: in the rst, the minimum interconnect delay i...
This tutorial introduces several methods of formal hardware verication that could potentially have a practical impact on the design process. The measure of success in integrating...
-- In this paper we present a new method for Boolean matching of completely specified Boolean functions. The canonical Generalized Reed-Muller forms are used as a powerful analysis...
Abstract - We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner a...
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay specications of manufactured circui...