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DFT
1997
IEEE
13 years 9 months ago
1997
IEEE
VTS
1997
IEEE
13 years 9 months ago
1997
IEEE
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
DFT
1997
IEEE
13 years 9 months ago
1997
IEEE
Recent increases in the density and size of memory ICs made it ne cessary to search for new defect tolerance techniques since the traditional methods are no longer e ective enough...
DFT
1997
IEEE
13 years 9 months ago
1997
IEEE
Crosstalk has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits...
DFT
1997
IEEE
13 years 9 months ago
1997
IEEE
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evalua...