Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs

Recent increases in the density and size of memory ICs made it ne cessary to search for new defect tolerance techniques since the traditional methods are no longer e ective enough. Several new such schemes have been recently proposed and implemented. Due to the high complexity of these new techniques compared to the simple row and column redundancy, Monte-Carlo simulations wer e used to evaluate their yield enhancement. In this paper we present a yield analysis of one such new design and compare its yield to that of the traditional design.

• Type: Conference
• Year: 1997
• Where: DFT
• Authors: Israel Koren, Zahava Koren
• Keywords: DFT 1997, Memory Ics, VLSI, Yield Analysis, Yield Enhancement