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DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 10 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
PRL
2007
107views more  PRL 2007»
13 years 4 months ago
Robust SS watermarking with improved capacity
Robustness is a key attribute of spread spectrum (SS) watermarking scheme. It is significantly deteriorated if one tries to achieve high embedding rate keeping other parameters u...
Santi P. Maity, Malay K. Kundu, Tirtha S. Das
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
13 years 10 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
14 years 1 months ago
Exploring linear structures of critical path delay faults to reduce test efforts
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou
CDES
2006
99views Hardware» more  CDES 2006»
13 years 6 months ago
Teraflop Computing for Nanoscience
: Over the last three decades there has been significant progress in the first principles methods for calculating the properties of materials at the quantum level. They have largel...
Yang Wang 0008, G. M. Stocks, Aurelian Rusanu, D. ...