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FDL
2007
IEEE
13 years 11 months ago
Time Modeling in MARTE
This article introduces the Time Model subprofile of MARTE, a new OMG UML Profile dedicated to Modeling and Analysis of Real-Time and Embedded systems. After a brief presentatio...
Robert de Simone, Charles André
FDL
2007
IEEE
13 years 11 months ago
An Integrated SystemC Debugging Environment
Since its first release the system level language SystemC had a significant impact on various areas in VLSI-CAD. One remarkable benefit of SystemC lies in the of abstraction le...
Frank Rogin, Christian Genz, Rolf Drechsler, Steff...
FDL
2007
IEEE
13 years 11 months ago
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
The system description language SystemC enables to quickly create executable specifications at adequate levbstraction for both hardware/software integration and fast design space...
Daniel Große, Hernan Peraza, Wolfgang Klinga...
FDL
2007
IEEE
13 years 11 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
FDL
2007
IEEE
13 years 8 months ago
A Metamodeling based Framework for Architectural Modeling and Simulator Generation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. The informal specification document from which the various collaterals are ...
Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shu...