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EURODAC
1995
IEEE
133views VHDL» more  EURODAC 1995»
13 years 9 months ago
Tree restructuring approach to mapping problem in cellular-architecture FPGAs
A new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity a...
Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Nav...
EURODAC
1995
IEEE
159views VHDL» more  EURODAC 1995»
13 years 9 months ago
Performance-oriented placement and routing for field-programmable gate arrays
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and glo...
Michael J. Alexander, James P. Cohoon, Joseph L. G...
FPL
1995
Springer
129views Hardware» more  FPL 1995»
13 years 9 months ago
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
Abstract. FPGAs have been proposed as high-performance alternatives to DSP processors. This paper quantitatively compares FPGA performance against DSP processors and ASICs using ac...
Russell J. Petersen, Brad L. Hutchings
FPGA
1995
ACM
118views FPGA» more  FPGA 1995»
13 years 9 months ago
An SBus Monitor Board
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
13 years 9 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu