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FPL
2001
Springer
92views Hardware» more  FPL 2001»
13 years 9 months ago
Evaluation of an FPGA Implementation of the Discrete Element Method
Benjamin Carrión Schäfer, Steven F. Qu...
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
13 years 9 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 1 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
13 years 9 months ago
Detailed routing architectures for embedded programmable logic IP cores
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be real...
Peter Hallschmid, Steven J. E. Wilton
FPGA
2001
ACM
128views FPGA» more  FPGA 2001»
13 years 9 months ago
Using sparse crossbars within LUT
In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, bu...
Guy G. Lemieux, David M. Lewis