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FPT
2005
IEEE
127views Hardware» more  FPT 2005»
13 years 10 months ago
Pipelining Saturated Accumulation
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipeli...
Karl Papadantonakis, Nachiket Kapre, Stephanie Cha...
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
13 years 10 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
FPT
2005
IEEE
170views Hardware» more  FPT 2005»
13 years 10 months ago
High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences
This paper describes a class of FPGA-specific uniform random number generators with a 2k −1 length period, which can provide k random bits per-cycle for the cost of k Lookup Ta...
David B. Thomas, Wayne Luk
FPT
2005
IEEE
117views Hardware» more  FPT 2005»
13 years 10 months ago
FPGA Defect Tolerance: Impact of Granularity
As device sizes shrink, FPGAs are increasingly prone to manufacturing defects. The ability to tolerate multiple defects is anticipated to be very important at 45nm and beyond. One...
Anthony J. Yu, Guy G. Lemieux
FPT
2005
IEEE
142views Hardware» more  FPT 2005»
13 years 10 months ago
Custom Hardware Architectures for Posture Analysis
This paper describes the design and implementation of hardware architectures for posture analysis. Posture analysis is an active research area in computer vision. It can be used i...
M. P. T. Juvonen, José Gabriel F. Coutinho,...