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GLVLSI
2000
IEEE
83views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Formal hardware verification by integrating HOL and MDG
V. K. Pisini, Sofiène Tahar, Paul Curzon, O...
GLVLSI
2000
IEEE
92views VLSI» more  GLVLSI 2000»
13 years 10 months ago
SPARTA: Simulation of Physics on a Real-Time Architecture
Abstract - In this paper, we discuss hardware acceleration for real-time physical modeling that would allow for realistic virtual environments. Additionally, we propose algorithms ...
Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irw...
GLVLSI
2000
IEEE
90views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Low power high speed analog-to-digital converter for wireless communications
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
A. E. Hussein, Mohamed I. Elmasry
GLVLSI
2000
IEEE
75views VLSI» more  GLVLSI 2000»
13 years 10 months ago
A wave-pipelined router architecture using ternary associative memory
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time an...
José G. Delgado-Frias, Jabulani Nyathi, Lax...
GLVLSI
2000
IEEE
105views VLSI» more  GLVLSI 2000»
13 years 10 months ago
An evolutionary approach to timing driven FPGA placement
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...
R. Venkatraman, Lalit M. Patnaik