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GLVLSI
2005
IEEE
125views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Low-power circuits using dynamic threshold devices
We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and perfor...
Paul Beckett
GLVLSI
2005
IEEE
103views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Causal probabilistic input dependency learning for switching model in VLSI circuits
Switching model captures the data-driven uncertainty in logic circuits in a comprehensive probabilistic framework. Switching is a critical factor that influences dynamic, active ...
Nirmal Ramalingam, Sanjukta Bhanja
GLVLSI
2005
IEEE
133views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Generating decision regions in analog measurement spaces
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Increasing design space of the instruction queue with tag coding
The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instruct...
Junwei Zhou, Andrew Mason
GLVLSI
2005
IEEE
199views VLSI» more  GLVLSI 2005»
13 years 10 months ago
Interconnect delay minimization through interlayer via placement in 3-D ICs
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
Vasilis F. Pavlidis, Eby G. Friedman