Increasing design space of the instruction queue with tag coding

The instruction queue is a critical component and performance bottleneck in superscalar microprocessors. Conventional designs use physical register identifiers to wake up instructions. This paper proposes decoupling the tags for instruction wakeup from the tags for physical register access, thus increasing the design space of the instruction queue by encoding its operand tags. Two coding methods have been developed. One uses a linear code to increase the Hamming distance between tags, reducing the tag match delay by more than 50% and achieving 12% improvement in the total wakeup/select delay for TSMC 0.18µm technology at

• Type: Conference
• Year: 2005
• Where: GLVLSI
• Authors: Junwei Zhou, Andrew Mason
• Keywords: GLVLSI 2005, Instruction Queue, Physical Register, Physical Register Identifiers, VLSI