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10

GLVLSI
2005
IEEE

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Low-power circuits using dynamic threshold devices

13 years 10 months ago

Low-power circuits using dynamic threshold devices

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We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and performance by dynamically shifting the threshold voltage during operation. A small number of simple circuits are analyzed and it is demonstrated that subthreshold power can be reduced by a factor in excess of 103 for these examples. Categories and Subject Descriptors B.7.1 [INTEGRATED CIRCUITS] Types and Design Styles – Advanced technologies, VLSI. General Terms Design. Keywords Subthreshold leakage, double-gate, thin-body, SOI, silicide, CMOS, nanotechnology.

Paul Beckett

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GLVLSI 2005 | Keywords Subthreshold Leakage | Static Power Loss | Ultra-thin Body | VLSI |

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Added	24 Jun 2010
Updated	24 Jun 2010
Type	Conference
Year	2005
Where	GLVLSI
Authors	Paul Beckett

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